-----------------------------------------------------------
--Archivo: vector_element.vhd		                 --
--Fecha de creación: 05/02/2011				 --
--Última fecha de modificación: 11/02/2011		 --
--Diseñador: Typson Sanchez				 --
--Diseño: Modulo de Memoria.				 --
--Propósito:Modulo de 64 elementos para el almacenamiento--
--en la memoria				 		 --
-----------------------------------------------------------
entity vector_element is
  port(
    DATA_I                 : in  std_logic_vector(3 downto 0);
    WRITE_ENABLE           : in  std_logic;
    CLK                    : in  std_logic;
    ADDRESS		           : in  std_logic_vector(5 downto 0);
    DATA_O                 : out std_logic_vector(3 downto 0)
  );
end vector_element;

architecture structural of vector_element is
   
  component element
    port(
      DATAIN          : in std_logic_vector(3 downto 0);
      ELEMENT_ENABLE  : in  std_logic;
      WRITE_ENABLE    : in  std_logic;
      CLK             : in  std_logic;
      DATAOUT         : out std_logic_vector(3 downto 0)
    );
  end component;

  component decoder_6
    port ( 
        SEL    : in  std_logic_vector (5 downto 0);
        outlet : out std_logic_vector (63 downto 0)
    );
  end component;

  component mux_64
    port (
	aa : in  std_logic_vector (3 downto 0);
	ab : in  std_logic_vector (3 downto 0);
	ac : in  std_logic_vector (3 downto 0);
	ad : in  std_logic_vector (3 downto 0);
	ae : in  std_logic_vector (3 downto 0);
	af : in  std_logic_vector (3 downto 0);
	ag : in  std_logic_vector (3 downto 0);
	ah : in  std_logic_vector (3 downto 0);
	ai : in  std_logic_vector (3 downto 0);
	aj : in  std_logic_vector (3 downto 0);
	ak : in  std_logic_vector (3 downto 0);
	al : in  std_logic_vector (3 downto 0);
	am : in  std_logic_vector (3 downto 0);
	an : in  std_logic_vector (3 downto 0);
	ao : in  std_logic_vector (3 downto 0);
	ap : in  std_logic_vector (3 downto 0);
	aq : in  std_logic_vector (3 downto 0);
	ar : in  std_logic_vector (3 downto 0);
	as : in  std_logic_vector (3 downto 0);
	at : in  std_logic_vector (3 downto 0);
	au : in  std_logic_vector (3 downto 0);
	av : in  std_logic_vector (3 downto 0);
	aw : in  std_logic_vector (3 downto 0);
	ax : in  std_logic_vector (3 downto 0);
	ay : in  std_logic_vector (3 downto 0);
	az : in  std_logic_vector (3 downto 0);
	ba : in  std_logic_vector (3 downto 0);
	bb : in  std_logic_vector (3 downto 0);
	bc : in  std_logic_vector (3 downto 0);
	bd : in  std_logic_vector (3 downto 0);
	be : in  std_logic_vector (3 downto 0);
	bf : in  std_logic_vector (3 downto 0);
	bg : in  std_logic_vector (3 downto 0);
	bh : in  std_logic_vector (3 downto 0);
	bi : in  std_logic_vector (3 downto 0);
	bj : in  std_logic_vector (3 downto 0);
	bk : in  std_logic_vector (3 downto 0);
	bl : in  std_logic_vector (3 downto 0);
	bm : in  std_logic_vector (3 downto 0);
	bn : in  std_logic_vector (3 downto 0);
	bo : in  std_logic_vector (3 downto 0);
	bp : in  std_logic_vector (3 downto 0);
	bq : in  std_logic_vector (3 downto 0);
	br : in  std_logic_vector (3 downto 0);
	bs : in  std_logic_vector (3 downto 0);
	bt : in  std_logic_vector (3 downto 0);
	bu : in  std_logic_vector (3 downto 0);
	bv : in  std_logic_vector (3 downto 0);
	bw : in  std_logic_vector (3 downto 0);
	bx : in  std_logic_vector (3 downto 0);
	by : in  std_logic_vector (3 downto 0);
	bz : in  std_logic_vector (3 downto 0);
	ca : in  std_logic_vector (3 downto 0);
	cb : in  std_logic_vector (3 downto 0);
	cc : in  std_logic_vector (3 downto 0);
	cd : in  std_logic_vector (3 downto 0);
	ce : in  std_logic_vector (3 downto 0);
	cf : in  std_logic_vector (3 downto 0);
	cg : in  std_logic_vector (3 downto 0);
	ch : in  std_logic_vector (3 downto 0);
	ci : in  std_logic_vector (3 downto 0);
	cj : in  std_logic_vector (3 downto 0);
	ck : in  std_logic_vector (3 downto 0);
	cl : in  std_logic_vector (3 downto 0);
    	s : in  std_logic_vector (5 downto 0); 
    	o : out std_logic_vector (3 downto 0)
  	); 
  end component;

  signal decoder_o: std_logic_vector(63 downto 0);
  signal data_tmp: std_logic_vector(3 downto 0);
  signal aa0 :  std_logic_vector (3 downto 0);
  signal ab0 :  std_logic_vector (3 downto 0);
  signal ac0 :  std_logic_vector (3 downto 0);
  signal ad0 :  std_logic_vector (3 downto 0);
  signal ae0 :  std_logic_vector (3 downto 0);
  signal af0 :  std_logic_vector (3 downto 0);
  signal ag0 :  std_logic_vector (3 downto 0);
  signal ah0 :  std_logic_vector (3 downto 0);
  signal ai0 :  std_logic_vector (3 downto 0);
  signal aj0 :  std_logic_vector (3 downto 0);
  signal ak0 :  std_logic_vector (3 downto 0);
  signal al0 :  std_logic_vector (3 downto 0);
  signal am0 :  std_logic_vector (3 downto 0);
  signal an0 :  std_logic_vector (3 downto 0);
  signal ao0 :  std_logic_vector (3 downto 0);
  signal ap0 :  std_logic_vector (3 downto 0);
  signal aq0 :  std_logic_vector (3 downto 0);
  signal ar0 :  std_logic_vector (3 downto 0);
  signal as0 :  std_logic_vector (3 downto 0);
  signal at0 :  std_logic_vector (3 downto 0);
  signal au0 :  std_logic_vector (3 downto 0);
  signal av0 :  std_logic_vector (3 downto 0);
  signal aw0 :  std_logic_vector (3 downto 0);
  signal ax0 :  std_logic_vector (3 downto 0);
  signal ay0 :  std_logic_vector (3 downto 0);
  signal az0 :  std_logic_vector (3 downto 0);
  signal ba0 :  std_logic_vector (3 downto 0);
  signal bb0 :  std_logic_vector (3 downto 0);
  signal bc0 :  std_logic_vector (3 downto 0);
  signal bd0 :  std_logic_vector (3 downto 0);
  signal be0 :  std_logic_vector (3 downto 0);
  signal bf0 :  std_logic_vector (3 downto 0);
  signal bg0 :  std_logic_vector (3 downto 0);
  signal bh0 :  std_logic_vector (3 downto 0);
  signal bi0 :  std_logic_vector (3 downto 0);
  signal bj0 :  std_logic_vector (3 downto 0);
  signal bk0 :  std_logic_vector (3 downto 0);
  signal bl0 :  std_logic_vector (3 downto 0);
  signal bm0 :  std_logic_vector (3 downto 0);
  signal bn0 :  std_logic_vector (3 downto 0);
  signal bo0 :  std_logic_vector (3 downto 0);
  signal bp0 :  std_logic_vector (3 downto 0);
  signal bq0 :  std_logic_vector (3 downto 0);
  signal br0 :  std_logic_vector (3 downto 0);
  signal bs0 :  std_logic_vector (3 downto 0);
  signal bt0 :  std_logic_vector (3 downto 0);
  signal bu0 :  std_logic_vector (3 downto 0);
  signal bv0 :  std_logic_vector (3 downto 0);
  signal bw0 :  std_logic_vector (3 downto 0);
  signal bx0 :  std_logic_vector (3 downto 0);
  signal by0 :  std_logic_vector (3 downto 0);
  signal bz0 :  std_logic_vector (3 downto 0);
  signal ca0 :  std_logic_vector (3 downto 0);
  signal cb0 :  std_logic_vector (3 downto 0);
  signal cc0 :  std_logic_vector (3 downto 0);
  signal cd0 :  std_logic_vector (3 downto 0);
  signal ce0 :  std_logic_vector (3 downto 0);
  signal cf0 :  std_logic_vector (3 downto 0);
  signal cg0 :  std_logic_vector (3 downto 0);
  signal ch0 :  std_logic_vector (3 downto 0);
  signal ci0 :  std_logic_vector (3 downto 0);
  signal cj0 :  std_logic_vector (3 downto 0);
  signal ck0 :  std_logic_vector (3 downto 0);
  signal cl0 :  std_logic_vector (3 downto 0); 

begin

  decoder_0 : decoder_6 port map(
     SEL    => ADDRESS,
     outlet => decoder_o
  );

  element0: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(0),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => aa0
  );

  element1: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(1),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ab0
  );

  element2: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(2),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ac0
  );

  element3: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(3),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ad0
  );

  element4: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(4),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ae0
  );
  element5: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(5),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => af0
  );
  element6: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(6),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ag0
  );
  element7: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(7),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ah0
  );

  element8: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(8),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ai0
  );

  element9: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(9),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => aj0
  );

  element10: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(10),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ak0
  );

  element11: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(11),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => al0
  );

  element12: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(12),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => am0
  );
  element13: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(13),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => an0
  );
  element14: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(14),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ao0
  );
  element15: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(15),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ap0
  );

  element16: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(16),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => aq0
  );

  element17: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(17),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ar0
  );

  element18: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(18),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => as0
  );

  element19: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(19),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => at0
  );

  element20: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(20),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => au0
  );
  element21: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(21),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => av0
  );
  element22: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(22),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => aw0
  );
  element23: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(23),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ax0
  );

  element24: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(24),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ay0
  );

  element25: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(25),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => az0
  );

  element26: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(26),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ba0
  );

  element27: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(27),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bb0
  );

  element28: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(28),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bc0
  );

  element29: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(29),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bd0
  );

  element30: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(30),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => be0
  );

  element31: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(31),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bf0
  );

  element32: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(32),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bg0
  );

  element33: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(33),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bh0
  );

  element34: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(34),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bi0
  );

  element35: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(35),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bj0
  );

  element36: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(36),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bk0
  );

  element37: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(37),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bl0
  );

  element38: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(38),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bm0
  );

  element39: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(39),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bn0
  );

  element40: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(40),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bo0
  );

  element41: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(41),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bp0
  );

  element42: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(42),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bq0
  );

  element43: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(43),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => br0
  );

  element44: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(44),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bs0
  );

  element45: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(45),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bt0
  );

  element46: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(46),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bu0
  );

  element47: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(47),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bv0
  );

  element48: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(48),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bw0
  );

  element49: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(49),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bx0
  );

  element50: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(50),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => by0
  );

  element51: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(51),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => bz0
  );

  element52: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(52),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ca0
  );

  element53: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(53),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => cb0
  );

  element54: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(54),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => cc0
  );

  element55: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(55),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => cd0
  );

  element56: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(56),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ce0
  );

  element57: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(57),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => cf0
  );

  element58: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(58),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => cg0
  );

  element59: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(59),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ch0
  );

  element60: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(60),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ci0
  );

  element61: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(61),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => cj0
  );

  element62: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(62),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => ck0
  );

  element63: element port map(
     DATAIN         => DATA_I,
     ELEMENT_ENABLE => decoder_o(63),
     WRITE_ENABLE   => WRITE_ENABLE,
     CLK            => CLK,
     DATAOUT        => cl0
  );

  mux_1 : mux_64 port map(
    aa => aa0, 
    ab => ab0,
    ac => ac0,
    ad => ad0,
    ae => ae0,
    af => af0,
    ag => ag0,
    ah => ah0,
    ai => ai0,
    aj => aj0,
    ak => ak0,
    al => al0,
    am => am0,
    an => an0,
    ao => ao0,
    ap => ap0,
    aq => aq0,
    ar => ar0,
    as => as0,
    at => at0,
    au => au0,
    av => av0,
    aw => aw0,
    ax => ax0,
    ay => ay0,
    az => az0,
    ba => ba0,
    bb => bb0,
    bc => bc0,
    bd => bd0,
    be => be0,
    bf => bf0,
    bg => bg0,
    bh => bh0,
    bi => bi0,
    bj => bj0,
    bk => bk0,
    bl => bl0,
    bm => bm0,
    bn => bn0,
    bo => bo0,
    bp => bp0,
    bq => bq0,
    br => br0,
    bs => bs0,
    bt => bt0,
    bu => bu0,
    bv => bv0,
    bw => bw0,
    bx => bx0,
    by => by0,
    bz => bz0,
    ca => ca0,
    cb => cb0,
    cc => cc0,
    cd => cd0,
    ce => ce0,
    cf => cf0,
    cg => cg0,
    ch => ch0,
    ci => ci0,
    cj => cj0,
    ck => ck0,
    cl => cl0,
    s => ADDRESS, 
    o => DATA_O
  );

end structural;
